Since the late 1960s, a new generation of integrated circuits has been developed approximately every four years. Each generation has been characterized by a halving of device dimensions, resulting in a four-fold density increase over the preceding generation. Increases in circuit density have been consistently limited by the resolution of the available photolithographic equipment. The minimum size of features and spaces that a given piece of photolithographic equipment can produce is directly related to its resolution capability. The sum of minimum feature width (F) and minimum space width (S) producible with a given piece of photolithographic equipment is referred to in this disclosure as "minimum pitch". Since, for practical purposes, F can be considered to be equal to S, minimum pitch is, therefore, approximately equal to double the minimum feature width, or 2F. Using contemporary photolithography techniques, one line (feature) and one space may be defined for a given minimum pitch.
It has long been recognized, by those skilled in the fabrication of integrated circuits, that vertical film layers as thin as 0.01 .mu.m can be grown with a high degree of accuracy. By comparison, the minimum feature size, producible with the present generation of photolithography equipment used to produce 1-megabit SRAMs and 4-megabit DRAMs, is approximately 0.5 .mu.m. Therefore, utilizing contemporary equipment in conjunction with contemporary photolithography techniques, approximately 1.0 .mu.m (the minimum pitch) is required to define one line and one space.
Thin-film technology has been used to create integrated circuit structures having either reduced feature width or reduced space width. U.S. Pat. No. 4,419,809, issued to IBM Corp. employees Jacob Riseman and Paul Tsang, is exemplary of a process for reducing feature width. With this process, submicron MOSFET gates are formed by performing a plasma anisotropic (spacer) etch on a thin conformal layer deposited over a mandrel having substantially vertical sidewalls. An example of a process for reducing space width (S) is found in U.S. Pat. No. 4,256,514. Issued to Hans Pogge (also an employee of IBM Corporation), this patent describes a method for decreasing the width of a trenched region on a silicon substrate by depositing a thin conformal layer and then performing an anisotropic plasma etch which leaves spacers on the walls surrounding the trenched region.
If vertical thin film layers could be used to provide a repeating pattern of a feature and a space, which together total less than 2F (the minimum pitch of the utilized photolithographic process), minimum pitch could be effectively reduced, resulting in increased circuit density equal to the square of the reciprocal of the reduction factor.